REDUCTION OF BASAL PLANE DISLOCATIONS IN EPITAXIAL SiC USING AN IN-SITU ETCH PROCESS

ABSTRACT

A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.

This application claims the benefit of U.S. Provisional Application No.61/787,903, filed on Mar. 15, 2013. This application is acontinuation-in-part application of pending U.S. patent application SerNo. 12/860,844, filed on Aug. 20, 2010, which claims the benefit of U.S.Provisional Application No. 61/235,455, filed on Aug. 20, 2009. Theseapplications and all other publications or patent documents citedthroughout this application are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure is generally related to SiC epitaxial growth.

DESCRIPTION OF RELATED ART

Since the ABB (Asea Brown Boveri, Inc.—Sweden) power company disclosedthe forward voltage, V_(f), drift problem that degraded their PiN diodes(Lendenmann et al., Mater. Sci. Forum, 353-356 (2001) 727-730), it hasbeen well established that the V_(f) drift problem is due to stackingfaults that originate from basal plane dislocations (BPDs) and that theonly way to overcome this problem is to reduce the BPD density inlow-doped portions of the epitaxial layer that forms the active regionof SiC power devices. The major source of BPDs in the epitaxy is fromBPDs in the SiC substrate. At the start of epitaxial growth, 70-90% ofthe substrate BPDs are converted to threading edge dislocations (TEDs)and the resulting BPD density in the epitaxy is typically in the100-1000 cm⁻² range; a further reduction to <1 cm⁻² is required fordevice production, based on the area of desired devices. For devicesrequiring higher power, the problem of BPDs becomes exacerbated sincethese devices require larger areas and hence further reduction of BPDsis essential.

Several techniques have been developed to decrease BPD density in theepitaxy. One technique uses a growth interrupt to turn the BPDs intoTEDs (VanMil et al., PCSI (2008); U.S. Pat. No. 8,652,255). Two othertechniques alter the wafer surface before epitaxial growth. The first isa surface patterning process that was originally developed and patentedby ABB and later used by Cree (Sumakeris et al., Mater. Sci. Forum,527-529 (2006) 141-146). The second is a process that involves KOHetching, epitaxial growth, and repolishing. It was developed andpatented by Cree. Cree has tested both processes and found the KOHetching method to be more effective (Sumakeris Id.). Another techniqueis to grow the epitaxial layers on wafers with an offcut angle lowerthan the standard 8° angle used for 4H-SiC (Chen et al., J. Appl. Phys.98 (2005) 114907). The tradeoff is that lowering the offcut angle tendsto introduce 3C inclusions that degrade device performance (Kojima etal., J. Cryst. Growth, 269 (2004) 367-376). Growth on 4° offcutsubstrates has also been demonstrated to convert BPDs to TEDs throughoutthe epitaxial growth process (U.S. Patent Appl. Pub. No. 2011/0045281).

BRIEF SUMMARY

Disclosed herein is a method comprising: providing an off-axis siliconcarbide substrate; and etching the surface of the substrate with a drygas, hydrogen, or an inert gas.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention will be readily obtainedby reference to the following Description of the Example Embodiments andthe accompanying drawings.

FIG. 1 shows a UVPL image of UID film showing various lengths of BPDs;C=continued, T=turned (converted to TED). Image sizes are 3 mm×3 mm.

FIG. 2 shows BPD density as a function of etch temperature

FIG. 3 shows BPD density as a function of etch pressure.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In the following description, for purposes of explanation and notlimitation, specific details are set forth in order to provide athorough understanding of the present disclosure. However, it will beapparent to one skilled in the art that the present subject matter maybe practiced in other embodiments that depart from these specificdetails. In other instances, detailed descriptions of well-known methodsand devices are omitted so as to not obscure the present disclosure withunnecessary detail.

The method may be employed in a wide range of bipolar SiC devicetechnologies enabling them to achieve higher performance levels. Suchdevices range from power diodes and switches to rf transistors and UVphotodetectors. The purpose of using a hydrogen etch prior to a SiCepitaxial growth process on 4° off-axis substrates is to reduce BPDswithin the active regions of SiC devices leading to improved deviceperformance and reliability. The etch process is used to increase theconversion of basal plane dislocations into threading edge dislocationsand have the converted BPDs

in a thin highly doped buffer layer. It has been demonstrated that BPDscause increasing forward voltage drift in bipolar SiC devices and thereare also reports in the literature that they can degrade majoritycarrier mobility and increase reverse-biased leakage (Agarwal et al.,Elec. Dev. Lett., 28 (2007) 587). BPD reduction processes that utilizeepitaxial growth are all based on the principle of converting BPDs intoTEDs, which have negligible adverse effects on the SiC devices.

In the disclosed method an off-axis silicon carbide substrate is used,which may be, for example, a 4H-SiC substrate or a 6H-SiC substrate. Theoff angle may be, but is not limited to, 4-8° . The surface of thesubstrate is then etched with a dry gas, hydrogen, or an inert gas, suchas argon. The gas may include a halogen or silane addition, or mayexclude such additions. The etching may take place before any epitaxialgrowth or other processing steps. Suitable etching conditions include,but are not limited to, 1450-1800° C. or 1620-1665° C., 30-500 or 40-130mbar of the etching gas, and up to 5-90 minutes of etching.

After the etching, a doped buffer layer may be grown on the substrate.The buffer layer may be doped with, for example, N⁺⁻ and P⁺, may beabout 0.5-30 μm or 6.5-8 μm thick. An epitaxial silicon carbide layermay then be grown on the buffer layer.

To determine the efficacy of the method, investigations were carried outusing the following approach. To determine where the BPD converts to aTED in the epitaxial layer, 3 key ingredients are required: (1) thelength of the BPD photoluminescence image taken in the plan view, (2)the orientation of the surface with respect to the basal plane of thesample (also known as the off-cut angle), and (3) the thickness of theepitaxial layer. For the first, ultra-violet photoluminescence images(UVPL images) were obtained using well-established techniques previouslypublished (Stahlbush et al., Mater. Sci. Forum 556-55 (2007) 295). X-raydiffraction (XRD) rocking curve maps of the symmetric (0008) reflectionwere analyzed to determine the off-cut angle of the substrates. Themanufacturer labels the wafers off-cut on the substrate wafer carrier,however, this is not always the exact off-cut. Additionally, this angleis not typically constant across the wafers (100, 75, or 50 mm) due tolattice curvature associated with the manufacturing process of thewafers. With that in mind, the precise, spatially-resolved off-cut angledetermined from the XRD rocking curve measurement maps was used for eachsample in the NRL research investigation which typically consisted of aquartered 75 or 100 mm wafer to determine what a full length BPD wouldbe if it extended through to the epi surface. Finally, the third keyingredient was measuring the precise thickness of the epitaxial films,evaluated using Fourier transform infrared measurements. With (1), (2),and (3) and using standard geometry, the plan view length of a BPD couldbe converted to a z-axis distance that the BPD covered from thebeginning of growth to where it ends. If the distance is found to beless than that of the epitaxial layer thickness, then the BPD is knownto have converted in to a threading edge dislocation (TED). If thedistance is equal to that of the epitaxial layer thickness, then the BPDdid not convert to a TED in the epitaxial layer.

The injected carrier lifetimes of some of the samples were evaluatedusing room temperature time-resolved photoluminescence, were they variedfrom 1000 to 1800 ns. The surface roughness of a film may also influencethe device properties as well as make processing difficult; therefore,AFM analysis was also performed to determine surface roughness. Samplesinvestigated resulted in similar surface morphology, with a surfaceroughness of ˜3.0 nm RMS. Carrier concentrations were also measured onseveral of the samples using Hg probe CV measurements, where the netcarrier concentration was ≦2.5×10¹⁴ cm⁻³.

Table 1 summarizes the results of several experiments. The films wereeither unintentionally (UID) or intentionally doped (ID) net carrierconcentration <4×10¹⁴ cm⁻³ using a nitrogen source gas. All films weregrown at a temperature of ˜1600° C., pressure of 100 mbar and gas phasecarbon-to-silicon (C/Si) ratio of 1.55 using an Aixtron VP508 reactor.The temperature was ramped from room temperature to a temperature of1400° C. in a hydrogen atmosphere. At this time, either the pressure wasmaintained at 100 mbar, or it was adjusted to a value between 40 mbarand 130 mbar. The temperature was then ramped to the etch temperature(between 1620° C. and 1665° C.). Once the temperature was reached, anetch step took place prior to the growth of a highly doped N⁺ bufferlayer. The thickness of the buffer layer was ˜6.5 μm and wasincorporated prior to the low doped epilayer, with the exception of onebuffer layer thickness being ˜8 μm. All samples were ˜20 μm thick (notincluding buffer layers, where applicable) and were grown at ˜10 μm/h,except sample C1110829, which was 13 μm thick and no buffer layer wasgrown. Experiments were conducted where only an etch took place toevaluate the surface of the substrate and determine the etch rate. Itwas found that the etch rate varied time and temperature and is shown inTable 2. The conversion process, i.e. instituting the in-situ etch,prior to growth was carried out for an epitaxial layer. UVPL images ofthis sample were analyzed and showed after a 50 min etch at 1620° C., 70mbar and an 8.1 μm N⁺ buffer layer, there were 144 BPDs extending out ofthe buffer into the unintentionally doped 20 micron layer. Whendetermined by the UVPL method described above, the epitaxial layer mayhave less than 20, 10, 5, or 2 BPDs/cm² in the epitaxial layer orsurface, or less than any of the BPD densities shown in Table 1.

TABLE 1 Tabulation of basal plane dislocations conversion efficiency forepitaxial growth on 4° off-axis substrates Etch Time Etch T Etch P BLThickness Epi Thickness Sample ID Substrate (min) (° C.) (mbar) (μm)(μm) BPD BPD/cm² C1110820 BD1787-44-iv 50 1620 70 8.13 19.57 144 26.2C1110829 BD1796-51-iii 50 1620 70 0 12.81 218 39.6 C1110830 50 1620 70C1110927 BD1796-51-iv 50 1650 70 6.78 19.41 13 2.4 C2111017 BD1796-52-iv50 1665 70 6.5 18.5 10 1.8 C2111019 BD1796-52-ii 50 1665 70 C2111021ABD1796-52-iii 50 1665 70 C2111025A BD1787-40-i 50 1665 70 C2111109BD1787-40-ii 90 1665 70 6.6 18.9 65 11.8 C2120320 BD1787-40-iii 90 166540 6.7 19.2 145 26.4 C2111229 GW0608-10-iii 5 1620 100 C2120406ABD1787-40-iv 90 1665 100 73 13.3 C2120406B DA1090-52-ii 90 1665 100 40273 C2120504 DA1090-53-iii 90 1665 130 286 52 C2120709 DA1090-53-i 501650 70 C2130204 GT0011 50 1630 40 G2130206 GT0011 50 1630 70 6.5 19.761 5.3 C2130207 GT0011 50 1630 100 6.5 19.7 71 6.1 C2130208 GT0011 501630 130 6.5 19.7 203 17.5

TABLE 2 Amount of SiC removed during the hydrogen etch step Etch TimeEtch Temperature Etch Pressure Material (min) (° C.) (mbar) removed (μm)5 1620 70 0.45 50 1620 70 1.34 50 1665 70 3.13

The full length of continuous BPDs were determined using XRD rockingcurve maps and film thicknesses found by using FTIR measurements. Thespatially-resolved XRD maps were used to determine the accurate off-cutangle of each quarter wafer prior to growth. After growth, incorporatingthe spatially-resolved thickness measurements combined with the off-cutangle, the expected full length BPD was determined. The BPD lengths werethen measured from the UVPL images using the software program, “ImageJ”by measuring the horizontal length from left to right of the BPD, seeFIG. 1. The lengths of the BPDs were then tallied and the conversionefficiency (number of BPDs that have converted to threading edgedislocations) was based on comparing the actual length of each BPD tothe full length BPD. With the variation of lattice curvature across aquarter wafer, it was essential to obtain the precise measurement of theoff-cut angle across the substrate, combined with the accurate filmthickness to correctly identify the actual BPD full length and correctlyreveal the trend of BPDs converting to TEDs within the epilayer. Plotsof the BPD density as a function of etch temperature and pressure isshown in FIGS. 2 and 3. The temperature influences the conversion atelevated temperatures >1620° C. The pressure influences the conversionand is clearly seen in FIG. 3. There is an optimized pressure of 70-100mbar for higher conversion of BPDs.

This process for determining conversion efficiency is more accurate thanothers used in the field. Typically, the BPD density is found using KOHetching, which creates etch pits on the surface of the wafer, and thesepits are counted. A low BPD density that has been published in theliterature is 2.6 cm² using KOH etching (Chen et al., J. Appl. Phys. 98(2005) 114907). If the above samples had been investigated using KOHetching, the BPD density would be zero for the majority of the samples.However, from the UVPL images, it can be seen that the BPDs are turningthroughout the film on 4° off-cut substrates. By using the KOH etchingapproach, the number of BPDs in the active region may be much higherthan what is at the surface of the epilayer. This means that conclusionsgiven by prior investigations using the KOH etching approach are notaccurate and have only limited value in developing methods for BPDreduction. By employing the UVPL technique, the total number of BPD inthe entire active region is determined. Therefore, the result of 10 BPDsin the epilayer shown in Table 1 is significant.

A phenomenon called “step bunching” may influence the conversion of BPDsinto TEDs during the growth of epitaxial films on 4 degree off-cutsubstrates. The formation of multi-unit cell high surface steps maycreate a potential barrier to continued basal plane dislocationpropagation out of the substrate and that an energy balance may becreated that makes it more favorable for the BPD to convert to a TEDthan to continue propagating. Ha et al., J. Cryst. Growth 244 (2002)257-266 describes that the image force is the driving force of BPDconversion to TED, speculates that “when the critical distance is smallin the range of several bilayers or several nanometers, a dislocationcan see two surfaces of the step structure, the terrace and the step,which are different from the average off-axis surface. In this case, theconversion will depend on the step structure”. It is also reported thatone “can expect that a basal plane dislocation will be attracted by thesurface of the last one or two macro-steps and, that the ‘step facetmechanism’ . . . will be governing the dislocation conversion”.Therefore, a processing window that is a function of growth rate,doping, off-cut angle, C/Si ratio, temperature and pressure determinethe optimal condition for conversion rate. During the etching, etch pitsmay be formed on the surface and the BPDs may be converted to TEDs atthe pit.

A hydrogen etch process prior to the epitaxial growth process on 4°off-axis enables the conversion of BPDs into TEDs—making it extremelymanufacturable. It has been found experimentally that the BPDs convertto TEDs after the hydrogen etch process, followed by a thin, ˜6.5 μmhighly doped N⁺ buffer layer and the lowest density of BPDs was 1.8 cm⁻². The process is easy to implement into a manufacturable process.Growing the N⁺ buffer layer will enable one to bury the BPDs in athinner buffer layer, producing a BPD free active region. This is theoptimal situation as it will permit the economic realization of a widerange of high voltage, bipolar devices.

Other techniques that have been used to convert BPDs to TEDs duringepitaxial growth are the three mentioned in the Background Art above.The first is patterning the surface of the SiC wafer before theepitaxial growth, which increases the BPD-to-TED conversion at thebeginning of the growth. It has the tendency to increase otherdetrimental extended defects such as ingrown faults. The secondtechnique is to etch the wafer in molten KOH before epitaxial growth.This creates pits at each of the dislocations including the BPDs, andthis technique also increases the BPD-to-TED conversion at the beginningof the growth. However, the top of the growth surface remains pittedcreating challenges for device manufacturing. An initial layer is grownand the wafer is polished to restore a smooth surface. It should benoted that this latter technique involves handling and wafers polishingwhich significantly adds to the overall cost of the final product. Thethird technique from Chen and Capano is to use wafers with a smalleroffcut angle than the standard 8° angle. As with the previoustechniques, it increases the BPD-to-TED conversion at the beginning ofthe growth. The tradeoff is that lowering the offcut angle results instep bunching which is more difficult to control. Further, such growthscan lead to SiC polytype inclusions that are also device killers.

The reduction of BPDs relies on the conversion of BPDs to threading edgedislocations (TEDs) during the epitaxial growth process and/or thesubstrate/epilayer interface due to the etch process prior to growth asthe surface is modified during the etch to improve the conversion ofBPDs. The growth process includes a step that consists of ramping thetemperature from room temperature to growth temperature, during whichtime hydrogen is flowing. The etching takes place for a certain amountof time, after which the growth process takes place. There are manyparameters which may be varied during the ramp process and the growthprocess which may influence the BPD conversion efficiency and rate.

The following lists the specific process parameters which may bemanipulated to result in optimal BPD conversion.

-   -   1) Propane flow rate during ramp to etch temperature and etch        process—modifying the propane flow rate during ramp has been        shown experimentally to influence the number of initial BPDs at        the substrate/epilayer or buffer layer/epilayer interface        (Myers-Ward et al., Mat. Sci. Forum 615-617 (2009) 105108)    -   2) Silane flow rate during ramp to etch temperature and during        etch process—incorporate a silane flow during these steps    -   3) Temperature at which point the pressure is adjusted for the        etch process—vary the temperature at which point the pressure        for etch is modified to influence the BPD conversion    -   4) Temperature of etch step—vary the temperature during etch to        influence the effect of step bunching and/or etch pits on the        surface since this may be the key factor in converting BPDs into        TEDs    -   5) Incorporating a halogen during the etch process before        growth—Use the halogen to assist in etching the surface to        influence the conversion of BPDs    -   6) Using an inert gas instead of hydrogen—Use Ar instead of        hydrogen during the etch to control the surface of the material        prior to growth, or a mixture of inert gas plus hydrogen gas    -   7) Vary the amount of hydrogen flow during the etch        process—varying the flow will assist in modifying the surface to        achieve the desired surface for the highest conversion rate    -   8) Etch Time—vary the etch time to achieve highest conversion        rate    -   9) Pressure during etch—vary etch pressure to achieve highest        conversion rate    -   10) Initiation of growth—Initiate the growth differently after        the etch process

Obviously, many modifications and variations are possible in light ofthe above teachings. It is therefore to be understood that the claimedsubject matter may be practiced otherwise than as specificallydescribed. Any reference to claim elements in the singular, e.g., usingthe articles “a,” “an,” “the,” or “said” is not construed as limitingthe element to the singular.

What is claimed is:
 1. A method comprising: providing an off-axissilicon carbide substrate; and etching the surface of the substrate witha dry gas, hydrogen, or an inert gas.
 2. The method of claim 1, whereinthe substrate is a 4H-SiC substrate.
 3. The method of claim 1, whereinthe substrate is a 6H-SiC substrate
 4. The method of claim 1, whereinthe substrate is a 0-8° off-axis 4H-SiC substrate.
 5. The method ofclaim 1, wherein the etching is performed with hydrogen.
 6. The methodof claim 1, wherein the etching is performed with silane.
 7. The methodof claim 1, wherein the etching is performed with argon.
 8. The methodof claim 1, wherein the etching is performed at 1450-1800° C.
 9. Themethod of claim 1, wherein the etching is performed at 30-500 mbar ofthe dry gas.
 10. The method of claim 1, wherein the etching is performedfor up to 90 minutes.
 11. The method of claim 1, further comprising:growing a doped buffer layer on the substrate after the etching.
 12. Themethod of claim 11, wherein the doped buffer layer is doped with N⁺. 13.The method of claim 11, wherein the doped buffer layer is doped with P⁺.14. The method of claim 11, wherein the doped buffer layer is about0.5-30 μm thick.
 15. The method of claim 11, further comprising: growingan epitaxial silicon carbide layer on the doped buffer layer.